// $Module: disp $
// $RegisterBank Version: V 1.0.00 $
// $Author:  $
// $Date: Fri, 17 Sep 2021 03:22:16 PM $
//

//GEN REG ADDR/OFFSET/MASK
#define  DISP_REG_00  0x0
#define  DISP_REG_01  0x4
#define  DISP_REG_02  0x8
#define  DISP_REG_03  0xc
#define  DISP_REG_04  0x10
#define  DISP_REG_05  0x14
#define  DISP_REG_06  0x18
#define  DISP_REG_07  0x1c
#define  DISP_REG_08  0x20
#define  DISP_REG_12  0x30
#define  DISP_REG_13  0x34
#define  DISP_REG_14  0x38
#define  DISP_REG_15  0x3c
#define  DISP_REG_16  0x40
#define  DISP_REG_17  0x44
#define  DISP_REG_18  0x48
#define  DISP_REG_19  0x4c
#define  DISP_REG_20  0x50
#define  DISP_REG_21  0x54
#define  DISP_REG_22  0x58
#define  DISP_REG_23  0x5c
#define  DISP_REG_24  0x60
#define  DISP_REG_25  0x64
#define  DISP_REG_26  0x68
#define  DISP_REG_27  0x6c
#define  DISP_REG_28  0x70
#define  DISP_REG_29  0x74
#define  DISP_REG_30  0x78
#define  DISP_REG_31  0x7c
#define  DISP_REG_32  0x80
#define  DISP_REG_33  0x84
#define  DISP_REG_34  0x88
#define  DISP_REG_35  0x8c
#define  DISP_REG_36  0x90
#define  DISP_REG_37  0x94
#define  DISP_REG_38  0x98
#define  DISP_REG_39  0x9c
#define  DISP_REG_40  0xa0
#define  DISP_REG_41  0xa4
#define  DISP_REG_42  0xa8
#define  DISP_REG_43  0xac
#define  DISP_REG_AXI_ST  0xb0
#define  DISP_REG_CATCH  0xc0
#define  DISP_REG_CHK_CTRL  0xc4
#define  DISP_CHK_RD_OSD  0xc8
#define  DISP_CHK_RD_IMG  0xcc
#define  DISP_REG_3E  0xf8
#define  DISP_REG_3F  0xfc
#define  DISP_REG_IMG_BWL  0x100
#define  DISP_REG_GAMMA_CTRL  0x180
#define  DISP_REG_GAMMA_WR_LUT  0x184
#define  DISP_REG_GAMMA_RD_LUT  0x188
#define  DISP_REG_MCU_IF_CTRL  0x200
#define  DISP_REG_MCU_SW_CTRL  0x204
#define  DISP_REG_MCU_STATUS  0x208
#define  DISP_REG_HW_MCU_AUTO  0x210
#define  DISP_REG_HW_MCU_CMD  0x214
#define  DISP_REG_HW_MCU_CMD_0  0x218
#define  DISP_REG_HW_MCU_CMD_1  0x21c
#define  DISP_REG_HW_MCU_CMD_2  0x220
#define  DISP_REG_HW_MCU_CMD_3  0x224
#define  DISP_REG_HW_MCU_CMD_4  0x228
#define  DISP_REG_HW_MCU_CMD_5  0x22c
#define  DISP_REG_HW_MCU_CMD_6  0x230
#define  DISP_REG_HW_MCU_CMD_7  0x234
#define  DISP_REG_HW_MCU_OV  0x238
#define  DISP_REG_SRGB_CTRL  0x240
#define  DISP_REG_TGEN_LITE_SIZE  0x304
#define  DISP_REG_TGEN_LITE_VS  0x308
#define  DISP_REG_TGEN_LITE_HS  0x314
#define  DISP_REG_DISP_SEL   0x0
#define  DISP_REG_DISP_SEL_OFFSET 0
#define  DISP_REG_DISP_SEL_MASK   0x7
#define  DISP_REG_SYNC_MODE   0x0
#define  DISP_REG_SYNC_MODE_OFFSET 4
#define  DISP_REG_SYNC_MODE_MASK   0x10
#define  DISP_REG_VS_POL   0x0
#define  DISP_REG_VS_POL_OFFSET 5
#define  DISP_REG_VS_POL_MASK   0x20
#define  DISP_REG_HS_POL   0x0
#define  DISP_REG_HS_POL_OFFSET 6
#define  DISP_REG_HS_POL_MASK   0x40
#define  DISP_REG_TGEN_EN   0x0
#define  DISP_REG_TGEN_EN_OFFSET 7
#define  DISP_REG_TGEN_EN_MASK   0x80
#define  DISP_REG_VS_POL_LITE   0x0
#define  DISP_REG_VS_POL_LITE_OFFSET 9
#define  DISP_REG_VS_POL_LITE_MASK   0x200
#define  DISP_REG_HS_POL_LITE   0x0
#define  DISP_REG_HS_POL_LITE_OFFSET 10
#define  DISP_REG_HS_POL_LITE_MASK   0x400
#define  DISP_REG_TGEN_EN_LITE   0x0
#define  DISP_REG_TGEN_EN_LITE_OFFSET 11
#define  DISP_REG_TGEN_EN_LITE_MASK   0x800
#define  DISP_REG_FMT_SEL   0x0
#define  DISP_REG_FMT_SEL_OFFSET 12
#define  DISP_REG_FMT_SEL_MASK   0xf000
#define  DISP_REG_SW_UP   0x0
#define  DISP_REG_SW_UP_OFFSET 16
#define  DISP_REG_SW_UP_MASK   0x10000
#define  DISP_REG_MASK_UP   0x0
#define  DISP_REG_MASK_UP_OFFSET 17
#define  DISP_REG_MASK_UP_MASK   0x20000
#define  DISP_REG_SHRD_SEL   0x0
#define  DISP_REG_SHRD_SEL_OFFSET 18
#define  DISP_REG_SHRD_SEL_MASK   0x40000
#define  DISP_REG_TRIG_SEL   0x0
#define  DISP_REG_TRIG_SEL_OFFSET 20
#define  DISP_REG_TRIG_SEL_MASK   0x100000
#define  DISP_REG_FORCE_CLK_ENABLE   0x0
#define  DISP_REG_FORCE_CLK_ENABLE_OFFSET 31
#define  DISP_REG_FORCE_CLK_ENABLE_MASK   0x80000000
#define  DISP_REG_VTT   0x4
#define  DISP_REG_VTT_OFFSET 0
#define  DISP_REG_VTT_MASK   0x3fff
#define  DISP_REG_HTT   0x4
#define  DISP_REG_HTT_OFFSET 16
#define  DISP_REG_HTT_MASK   0x3fff0000
#define  DISP_REG_VS_STR   0x8
#define  DISP_REG_VS_STR_OFFSET 0
#define  DISP_REG_VS_STR_MASK   0x3fff
#define  DISP_REG_VS_STP   0x8
#define  DISP_REG_VS_STP_OFFSET 16
#define  DISP_REG_VS_STP_MASK   0x3fff0000
#define  DISP_REG_VFDE_STR   0xc
#define  DISP_REG_VFDE_STR_OFFSET 0
#define  DISP_REG_VFDE_STR_MASK   0x3fff
#define  DISP_REG_VFDE_STP   0xc
#define  DISP_REG_VFDE_STP_OFFSET 16
#define  DISP_REG_VFDE_STP_MASK   0x3fff0000
#define  DISP_REG_VMDE_STR   0x10
#define  DISP_REG_VMDE_STR_OFFSET 0
#define  DISP_REG_VMDE_STR_MASK   0x3fff
#define  DISP_REG_VMDE_STP   0x10
#define  DISP_REG_VMDE_STP_OFFSET 16
#define  DISP_REG_VMDE_STP_MASK   0x3fff0000
#define  DISP_REG_HS_STR   0x14
#define  DISP_REG_HS_STR_OFFSET 0
#define  DISP_REG_HS_STR_MASK   0x3fff
#define  DISP_REG_HS_STP   0x14
#define  DISP_REG_HS_STP_OFFSET 16
#define  DISP_REG_HS_STP_MASK   0x3fff0000
#define  DISP_REG_HFDE_STR   0x18
#define  DISP_REG_HFDE_STR_OFFSET 0
#define  DISP_REG_HFDE_STR_MASK   0x3fff
#define  DISP_REG_HFDE_STP   0x18
#define  DISP_REG_HFDE_STP_OFFSET 16
#define  DISP_REG_HFDE_STP_MASK   0x3fff0000
#define  DISP_REG_HMDE_STR   0x1c
#define  DISP_REG_HMDE_STR_OFFSET 0
#define  DISP_REG_HMDE_STR_MASK   0x3fff
#define  DISP_REG_HMDE_STP   0x1c
#define  DISP_REG_HMDE_STP_OFFSET 16
#define  DISP_REG_HMDE_STP_MASK   0x3fff0000
#define  DISP_REG_TRIG_STR   0x20
#define  DISP_REG_TRIG_STR_OFFSET 0
#define  DISP_REG_TRIG_STR_MASK   0x3fff
#define  DISP_REG_FIFO_RD_TH_Y   0x30
#define  DISP_REG_FIFO_RD_TH_Y_OFFSET 0
#define  DISP_REG_FIFO_RD_TH_Y_MASK   0xff
#define  DISP_REG_FIFO_PR_TH_Y   0x30
#define  DISP_REG_FIFO_PR_TH_Y_OFFSET 8
#define  DISP_REG_FIFO_PR_TH_Y_MASK   0xff00
#define  DISP_REG_FIFO_RD_TH_C   0x30
#define  DISP_REG_FIFO_RD_TH_C_OFFSET 16
#define  DISP_REG_FIFO_RD_TH_C_MASK   0xff0000
#define  DISP_REG_FIFO_PR_TH_C   0x30
#define  DISP_REG_FIFO_PR_TH_C_OFFSET 24
#define  DISP_REG_FIFO_PR_TH_C_MASK   0xff000000
#define  DISP_REG_SRC_Y_BASE_0   0x34
#define  DISP_REG_SRC_Y_BASE_0_OFFSET 0
#define  DISP_REG_SRC_Y_BASE_0_MASK   0xffffffff
#define  DISP_REG_SRC_Y_BASE_1   0x38
#define  DISP_REG_SRC_Y_BASE_1_OFFSET 0
#define  DISP_REG_SRC_Y_BASE_1_MASK   0xff
#define  DISP_REG_SRC_U_BASE_0   0x3c
#define  DISP_REG_SRC_U_BASE_0_OFFSET 0
#define  DISP_REG_SRC_U_BASE_0_MASK   0xffffffff
#define  DISP_REG_SRC_U_BASE_1   0x40
#define  DISP_REG_SRC_U_BASE_1_OFFSET 0
#define  DISP_REG_SRC_U_BASE_1_MASK   0xff
#define  DISP_REG_SRC_V_BASE_0   0x44
#define  DISP_REG_SRC_V_BASE_0_OFFSET 0
#define  DISP_REG_SRC_V_BASE_0_MASK   0xffffffff
#define  DISP_REG_SRC_V_BASE_1   0x48
#define  DISP_REG_SRC_V_BASE_1_OFFSET 0
#define  DISP_REG_SRC_V_BASE_1_MASK   0xff
#define  DISP_REG_SRC_Y_PITCH   0x4c
#define  DISP_REG_SRC_Y_PITCH_OFFSET 0
#define  DISP_REG_SRC_Y_PITCH_MASK   0xffffff
#define  DISP_REG_OS_MAX   0x4c
#define  DISP_REG_OS_MAX_OFFSET 24
#define  DISP_REG_OS_MAX_MASK   0xf000000
#define  DISP_REG_BURST_LN   0x4c
#define  DISP_REG_BURST_LN_OFFSET 28
#define  DISP_REG_BURST_LN_MASK   0xf0000000
#define  DISP_REG_SRC_C_PITCH   0x50
#define  DISP_REG_SRC_C_PITCH_OFFSET 0
#define  DISP_REG_SRC_C_PITCH_MASK   0xffffff
#define  DISP_REG_64B_ALIGN   0x50
#define  DISP_REG_64B_ALIGN_OFFSET 24
#define  DISP_REG_64B_ALIGN_MASK   0x1000000
#define  DISP_REG_SRC_X_STR   0x54
#define  DISP_REG_SRC_X_STR_OFFSET 0
#define  DISP_REG_SRC_X_STR_MASK   0xffff
#define  DISP_REG_SRC_Y_STR   0x54
#define  DISP_REG_SRC_Y_STR_OFFSET 16
#define  DISP_REG_SRC_Y_STR_MASK   0xffff0000
#define  DISP_REG_SRC_WD   0x58
#define  DISP_REG_SRC_WD_OFFSET 0
#define  DISP_REG_SRC_WD_MASK   0xffff
#define  DISP_REG_SRC_HT   0x58
#define  DISP_REG_SRC_HT_OFFSET 16
#define  DISP_REG_SRC_HT_MASK   0xffff0000
#define  DISP_REG_OUT_CSC_C00   0x5c
#define  DISP_REG_OUT_CSC_C00_OFFSET 0
#define  DISP_REG_OUT_CSC_C00_MASK   0x3fff
#define  DISP_REG_OUT_CSC_C01   0x5c
#define  DISP_REG_OUT_CSC_C01_OFFSET 16
#define  DISP_REG_OUT_CSC_C01_MASK   0x3fff0000
#define  DISP_REG_OUT_CSC_EN   0x5c
#define  DISP_REG_OUT_CSC_EN_OFFSET 31
#define  DISP_REG_OUT_CSC_EN_MASK   0x80000000
#define  DISP_REG_OUT_CSC_C02   0x60
#define  DISP_REG_OUT_CSC_C02_OFFSET 0
#define  DISP_REG_OUT_CSC_C02_MASK   0x3fff
#define  DISP_REG_OUT_CSC_C10   0x60
#define  DISP_REG_OUT_CSC_C10_OFFSET 16
#define  DISP_REG_OUT_CSC_C10_MASK   0x3fff0000
#define  DISP_REG_OUT_CSC_C11   0x64
#define  DISP_REG_OUT_CSC_C11_OFFSET 0
#define  DISP_REG_OUT_CSC_C11_MASK   0x3fff
#define  DISP_REG_OUT_CSC_C12   0x64
#define  DISP_REG_OUT_CSC_C12_OFFSET 16
#define  DISP_REG_OUT_CSC_C12_MASK   0x3fff0000
#define  DISP_REG_OUT_CSC_C20   0x68
#define  DISP_REG_OUT_CSC_C20_OFFSET 0
#define  DISP_REG_OUT_CSC_C20_MASK   0x3fff
#define  DISP_REG_OUT_CSC_C21   0x68
#define  DISP_REG_OUT_CSC_C21_OFFSET 16
#define  DISP_REG_OUT_CSC_C21_MASK   0x3fff0000
#define  DISP_REG_OUT_CSC_C22   0x6c
#define  DISP_REG_OUT_CSC_C22_OFFSET 0
#define  DISP_REG_OUT_CSC_C22_MASK   0x3fff
#define  DISP_REG_OUT_CSC_SUB_0   0x70
#define  DISP_REG_OUT_CSC_SUB_0_OFFSET 0
#define  DISP_REG_OUT_CSC_SUB_0_MASK   0xff
#define  DISP_REG_OUT_CSC_SUB_1   0x70
#define  DISP_REG_OUT_CSC_SUB_1_OFFSET 8
#define  DISP_REG_OUT_CSC_SUB_1_MASK   0xff00
#define  DISP_REG_OUT_CSC_SUB_2   0x70
#define  DISP_REG_OUT_CSC_SUB_2_OFFSET 16
#define  DISP_REG_OUT_CSC_SUB_2_MASK   0xff0000
#define  DISP_REG_OUT_CSC_ADD_0   0x74
#define  DISP_REG_OUT_CSC_ADD_0_OFFSET 0
#define  DISP_REG_OUT_CSC_ADD_0_MASK   0xff
#define  DISP_REG_OUT_CSC_ADD_1   0x74
#define  DISP_REG_OUT_CSC_ADD_1_OFFSET 8
#define  DISP_REG_OUT_CSC_ADD_1_MASK   0xff00
#define  DISP_REG_OUT_CSC_ADD_2   0x74
#define  DISP_REG_OUT_CSC_ADD_2_OFFSET 16
#define  DISP_REG_OUT_CSC_ADD_2_MASK   0xff0000
#define  DISP_REG_IN_CSC_C00   0x78
#define  DISP_REG_IN_CSC_C00_OFFSET 0
#define  DISP_REG_IN_CSC_C00_MASK   0x3fff
#define  DISP_REG_IN_CSC_C01   0x78
#define  DISP_REG_IN_CSC_C01_OFFSET 16
#define  DISP_REG_IN_CSC_C01_MASK   0x3fff0000
#define  DISP_REG_IN_CSC_EN   0x78
#define  DISP_REG_IN_CSC_EN_OFFSET 31
#define  DISP_REG_IN_CSC_EN_MASK   0x80000000
#define  DISP_REG_IN_CSC_C02   0x7c
#define  DISP_REG_IN_CSC_C02_OFFSET 0
#define  DISP_REG_IN_CSC_C02_MASK   0x3fff
#define  DISP_REG_IN_CSC_C10   0x7c
#define  DISP_REG_IN_CSC_C10_OFFSET 16
#define  DISP_REG_IN_CSC_C10_MASK   0x3fff0000
#define  DISP_REG_IN_CSC_C11   0x80
#define  DISP_REG_IN_CSC_C11_OFFSET 0
#define  DISP_REG_IN_CSC_C11_MASK   0x3fff
#define  DISP_REG_IN_CSC_C12   0x80
#define  DISP_REG_IN_CSC_C12_OFFSET 16
#define  DISP_REG_IN_CSC_C12_MASK   0x3fff0000
#define  DISP_REG_IN_CSC_C20   0x84
#define  DISP_REG_IN_CSC_C20_OFFSET 0
#define  DISP_REG_IN_CSC_C20_MASK   0x3fff
#define  DISP_REG_IN_CSC_C21   0x84
#define  DISP_REG_IN_CSC_C21_OFFSET 16
#define  DISP_REG_IN_CSC_C21_MASK   0x3fff0000
#define  DISP_REG_IN_CSC_C22   0x88
#define  DISP_REG_IN_CSC_C22_OFFSET 0
#define  DISP_REG_IN_CSC_C22_MASK   0x3fff
#define  DISP_REG_IN_CSC_SUB_0   0x8c
#define  DISP_REG_IN_CSC_SUB_0_OFFSET 0
#define  DISP_REG_IN_CSC_SUB_0_MASK   0xff
#define  DISP_REG_IN_CSC_SUB_1   0x8c
#define  DISP_REG_IN_CSC_SUB_1_OFFSET 8
#define  DISP_REG_IN_CSC_SUB_1_MASK   0xff00
#define  DISP_REG_IN_CSC_SUB_2   0x8c
#define  DISP_REG_IN_CSC_SUB_2_OFFSET 16
#define  DISP_REG_IN_CSC_SUB_2_MASK   0xff0000
#define  DISP_REG_IN_CSC_ADD_0   0x90
#define  DISP_REG_IN_CSC_ADD_0_OFFSET 0
#define  DISP_REG_IN_CSC_ADD_0_MASK   0xff
#define  DISP_REG_IN_CSC_ADD_1   0x90
#define  DISP_REG_IN_CSC_ADD_1_OFFSET 8
#define  DISP_REG_IN_CSC_ADD_1_MASK   0xff00
#define  DISP_REG_IN_CSC_ADD_2   0x90
#define  DISP_REG_IN_CSC_ADD_2_OFFSET 16
#define  DISP_REG_IN_CSC_ADD_2_MASK   0xff0000
#define  DISP_REG_GRA_INV   0x94
#define  DISP_REG_GRA_INV_OFFSET 0
#define  DISP_REG_GRA_INV_MASK   0x1
#define  DISP_REG_PAT_EN   0x94
#define  DISP_REG_PAT_EN_OFFSET 1
#define  DISP_REG_PAT_EN_MASK   0x2
#define  DISP_REG_AUTO_EN   0x94
#define  DISP_REG_AUTO_EN_OFFSET 2
#define  DISP_REG_AUTO_EN_MASK   0x4
#define  DISP_REG_DITH_EN   0x94
#define  DISP_REG_DITH_EN_OFFSET 3
#define  DISP_REG_DITH_EN_MASK   0x8
#define  DISP_REG_SNOW_EN   0x94
#define  DISP_REG_SNOW_EN_OFFSET 4
#define  DISP_REG_SNOW_EN_MASK   0x10
#define  DISP_REG_FIX_MC   0x94
#define  DISP_REG_FIX_MC_OFFSET 5
#define  DISP_REG_FIX_MC_MASK   0x20
#define  DISP_REG_DITH_MD   0x94
#define  DISP_REG_DITH_MD_OFFSET 8
#define  DISP_REG_DITH_MD_MASK   0x700
#define  DISP_REG_PAT_PRD   0x94
#define  DISP_REG_PAT_PRD_OFFSET 16
#define  DISP_REG_PAT_PRD_MASK   0xff0000
#define  DISP_REG_PAT_IDX   0x94
#define  DISP_REG_PAT_IDX_OFFSET 24
#define  DISP_REG_PAT_IDX_MASK   0x1f000000
#define  DISP_REG_PAT_R   0x98
#define  DISP_REG_PAT_R_OFFSET 0
#define  DISP_REG_PAT_R_MASK   0x3ff
#define  DISP_REG_PAT_G   0x98
#define  DISP_REG_PAT_G_OFFSET 16
#define  DISP_REG_PAT_G_MASK   0x3ff0000
#define  DISP_REG_PAT_B   0x9c
#define  DISP_REG_PAT_B_OFFSET 0
#define  DISP_REG_PAT_B_MASK   0x3ff
#define  DISP_REG_FDE_R   0x9c
#define  DISP_REG_FDE_R_OFFSET 16
#define  DISP_REG_FDE_R_MASK   0x3ff0000
#define  DISP_REG_FDE_G   0xa0
#define  DISP_REG_FDE_G_OFFSET 0
#define  DISP_REG_FDE_G_MASK   0x3ff
#define  DISP_REG_FDE_B   0xa0
#define  DISP_REG_FDE_B_OFFSET 16
#define  DISP_REG_FDE_B_MASK   0x3ff0000
#define  DISP_REG_MDE_R   0xa4
#define  DISP_REG_MDE_R_OFFSET 0
#define  DISP_REG_MDE_R_MASK   0x3ff
#define  DISP_REG_MDE_G   0xa4
#define  DISP_REG_MDE_G_OFFSET 16
#define  DISP_REG_MDE_G_MASK   0x3ff0000
#define  DISP_REG_MDE_B   0xa8
#define  DISP_REG_MDE_B_OFFSET 0
#define  DISP_REG_MDE_B_MASK   0x3ff
#define  DISP_REG_OUT_BIT   0xa8
#define  DISP_REG_OUT_BIT_OFFSET 16
#define  DISP_REG_OUT_BIT_MASK   0x30000
#define  DISP_REG_DROP_MD   0xa8
#define  DISP_REG_DROP_MD_OFFSET 18
#define  DISP_REG_DROP_MD_MASK   0xc0000
#define  DISP_REG_DISP_BW_FAIL   0xac
#define  DISP_REG_DISP_BW_FAIL_OFFSET 0
#define  DISP_REG_DISP_BW_FAIL_MASK   0x1
#define  DISP_REG_CLR_DISP_BW_FAIL   0xac
#define  DISP_REG_CLR_DISP_BW_FAIL_OFFSET 1
#define  DISP_REG_CLR_DISP_BW_FAIL_MASK   0x2
#define  DISP_REG_OSD_BW_FAIL   0xac
#define  DISP_REG_OSD_BW_FAIL_OFFSET 2
#define  DISP_REG_OSD_BW_FAIL_MASK   0x4
#define  DISP_REG_CLR_OSD_BW_FAIL   0xac
#define  DISP_REG_CLR_OSD_BW_FAIL_OFFSET 3
#define  DISP_REG_CLR_OSD_BW_FAIL_MASK   0x8
#define  DISP_REG_ERR_FWR_Y   0xac
#define  DISP_REG_ERR_FWR_Y_OFFSET 4
#define  DISP_REG_ERR_FWR_Y_MASK   0x10
#define  DISP_REG_ERR_FWR_U   0xac
#define  DISP_REG_ERR_FWR_U_OFFSET 5
#define  DISP_REG_ERR_FWR_U_MASK   0x20
#define  DISP_REG_ERR_FWR_V   0xac
#define  DISP_REG_ERR_FWR_V_OFFSET 6
#define  DISP_REG_ERR_FWR_V_MASK   0x40
#define  DISP_REG_CLR_FWR_1T   0xac
#define  DISP_REG_CLR_FWR_1T_OFFSET 7
#define  DISP_REG_CLR_FWR_1T_MASK   0x80
#define  DISP_REG_ERR_ERD_Y   0xac
#define  DISP_REG_ERR_ERD_Y_OFFSET 8
#define  DISP_REG_ERR_ERD_Y_MASK   0x100
#define  DISP_REG_ERR_ERD_U   0xac
#define  DISP_REG_ERR_ERD_U_OFFSET 9
#define  DISP_REG_ERR_ERD_U_MASK   0x200
#define  DISP_REG_ERR_ERD_V   0xac
#define  DISP_REG_ERR_ERD_V_OFFSET 10
#define  DISP_REG_ERR_ERD_V_MASK   0x400
#define  DISP_REG_CLR_ERD_1T   0xac
#define  DISP_REG_CLR_ERD_1T_OFFSET 11
#define  DISP_REG_CLR_ERD_1T_MASK   0x800
#define  DISP_REG_LB_FULL_Y   0xac
#define  DISP_REG_LB_FULL_Y_OFFSET 12
#define  DISP_REG_LB_FULL_Y_MASK   0x1000
#define  DISP_REG_LB_FULL_U   0xac
#define  DISP_REG_LB_FULL_U_OFFSET 13
#define  DISP_REG_LB_FULL_U_MASK   0x2000
#define  DISP_REG_LB_FULL_V   0xac
#define  DISP_REG_LB_FULL_V_OFFSET 14
#define  DISP_REG_LB_FULL_V_MASK   0x4000
#define  DISP_REG_LB_EMPTY_Y   0xac
#define  DISP_REG_LB_EMPTY_Y_OFFSET 16
#define  DISP_REG_LB_EMPTY_Y_MASK   0x10000
#define  DISP_REG_LB_EMPTY_U   0xac
#define  DISP_REG_LB_EMPTY_U_OFFSET 17
#define  DISP_REG_LB_EMPTY_U_MASK   0x20000
#define  DISP_REG_LB_EMPTY_V   0xac
#define  DISP_REG_LB_EMPTY_V_OFFSET 18
#define  DISP_REG_LB_EMPTY_V_MASK   0x40000
#define  DISP_REG_AXI_IDLE   0xb0
#define  DISP_REG_AXI_IDLE_OFFSET 0
#define  DISP_REG_AXI_IDLE_MASK   0x1
#define  DISP_REG_AXI_STATE   0xb0
#define  DISP_REG_AXI_STATE_OFFSET 8
#define  DISP_REG_AXI_STATE_MASK   0xff00
#define  DISP_REG_CATCH_MODE   0xc0
#define  DISP_REG_CATCH_MODE_OFFSET 0
#define  DISP_REG_CATCH_MODE_MASK   0x1
#define  DISP_REG_DMA_URGENT_EN   0xc0
#define  DISP_REG_DMA_URGENT_EN_OFFSET 1
#define  DISP_REG_DMA_URGENT_EN_MASK   0x2
#define  DISP_REG_QOS_SEL_RR   0xc0
#define  DISP_REG_QOS_SEL_RR_OFFSET 2
#define  DISP_REG_QOS_SEL_RR_MASK   0x4
#define  DISP_REG_CATCH_ACT_Y   0xc0
#define  DISP_REG_CATCH_ACT_Y_OFFSET 4
#define  DISP_REG_CATCH_ACT_Y_MASK   0x10
#define  DISP_REG_CATCH_ACT_U   0xc0
#define  DISP_REG_CATCH_ACT_U_OFFSET 5
#define  DISP_REG_CATCH_ACT_U_MASK   0x20
#define  DISP_REG_CATCH_ACT_V   0xc0
#define  DISP_REG_CATCH_ACT_V_OFFSET 6
#define  DISP_REG_CATCH_ACT_V_MASK   0x40
#define  DISP_REG_CATCH_FAIL_Y   0xc0
#define  DISP_REG_CATCH_FAIL_Y_OFFSET 8
#define  DISP_REG_CATCH_FAIL_Y_MASK   0x100
#define  DISP_REG_CATCH_FAIL_U   0xc0
#define  DISP_REG_CATCH_FAIL_U_OFFSET 9
#define  DISP_REG_CATCH_FAIL_U_MASK   0x200
#define  DISP_REG_CATCH_FAIL_V   0xc0
#define  DISP_REG_CATCH_FAIL_V_OFFSET 10
#define  DISP_REG_CATCH_FAIL_V_MASK   0x400
#define  DISP_REG_CHKSUM_DAT_IN   0xc4
#define  DISP_REG_CHKSUM_DAT_IN_OFFSET 0
#define  DISP_REG_CHKSUM_DAT_IN_MASK   0xff
#define  DISP_REG_CHKSUM_DAT_OUT   0xc4
#define  DISP_REG_CHKSUM_DAT_OUT_OFFSET 8
#define  DISP_REG_CHKSUM_DAT_OUT_MASK   0xff00
#define  DISP_REG_CHECKSUM_EN   0xc4
#define  DISP_REG_CHECKSUM_EN_OFFSET 31
#define  DISP_REG_CHECKSUM_EN_MASK   0x80000000
#define  DISP_REG_CHKSUM_AXI_OSD   0xc8
#define  DISP_REG_CHKSUM_AXI_OSD_OFFSET 0
#define  DISP_REG_CHKSUM_AXI_OSD_MASK   0xffffffff
#define  DISP_REG_CHKSUM_AXI_IMG   0xcc
#define  DISP_REG_CHKSUM_AXI_IMG_OFFSET 0
#define  DISP_REG_CHKSUM_AXI_IMG_MASK   0xffffffff
#define  DISP_REG_DUMMY   0xf8
#define  DISP_REG_DUMMY_OFFSET 0
#define  DISP_REG_DUMMY_MASK   0xffffffff
#define  DISP_REG_DUMMY_R0   0xfc
#define  DISP_REG_DUMMY_R0_OFFSET 0
#define  DISP_REG_DUMMY_R0_MASK   0xffffffff
#define  DISP_REG_IMG_BWL_WIN   0x100
#define  DISP_REG_IMG_BWL_WIN_OFFSET 0
#define  DISP_REG_IMG_BWL_WIN_MASK   0x3ff
#define  DISP_REG_IMG_BWL_VLD   0x100
#define  DISP_REG_IMG_BWL_VLD_OFFSET 16
#define  DISP_REG_IMG_BWL_VLD_MASK   0x3ff0000
#define  DISP_REG_IMG_BWL_EN   0x100
#define  DISP_REG_IMG_BWL_EN_OFFSET 31
#define  DISP_REG_IMG_BWL_EN_MASK   0x80000000
#define  DISP_REG_GAMMA_ACC_LUT   0x180
#define  DISP_REG_GAMMA_ACC_LUT_OFFSET 0
#define  DISP_REG_GAMMA_ACC_LUT_MASK   0x1
#define  DISP_REG_GAMMA_ACC_WR   0x180
#define  DISP_REG_GAMMA_ACC_WR_OFFSET 1
#define  DISP_REG_GAMMA_ACC_WR_MASK   0x2
#define  DISP_REG_GAMMA_EN   0x180
#define  DISP_REG_GAMMA_EN_OFFSET 2
#define  DISP_REG_GAMMA_EN_MASK   0x4
#define  DISP_REG_GAMMA_PRE_OSD   0x180
#define  DISP_REG_GAMMA_PRE_OSD_OFFSET 3
#define  DISP_REG_GAMMA_PRE_OSD_MASK   0x8
#define  DISP_REG_GAMMA_B_WDAT   0x184
#define  DISP_REG_GAMMA_B_WDAT_OFFSET 0
#define  DISP_REG_GAMMA_B_WDAT_MASK   0xff
#define  DISP_REG_GAMMA_G_WDAT   0x184
#define  DISP_REG_GAMMA_G_WDAT_OFFSET 8
#define  DISP_REG_GAMMA_G_WDAT_MASK   0xff00
#define  DISP_REG_GAMMA_R_WDAT   0x184
#define  DISP_REG_GAMMA_R_WDAT_OFFSET 16
#define  DISP_REG_GAMMA_R_WDAT_MASK   0xff0000
#define  DISP_REG_GAMMA_ADDR   0x184
#define  DISP_REG_GAMMA_ADDR_OFFSET 24
#define  DISP_REG_GAMMA_ADDR_MASK   0x7f000000
#define  DISP_REG_GAMMA_ACC_W1T   0x184
#define  DISP_REG_GAMMA_ACC_W1T_OFFSET 31
#define  DISP_REG_GAMMA_ACC_W1T_MASK   0x80000000
#define  DISP_REG_GAMMA_B_RDAT   0x188
#define  DISP_REG_GAMMA_B_RDAT_OFFSET 0
#define  DISP_REG_GAMMA_B_RDAT_MASK   0xff
#define  DISP_REG_GAMMA_G_RDAT   0x188
#define  DISP_REG_GAMMA_G_RDAT_OFFSET 8
#define  DISP_REG_GAMMA_G_RDAT_MASK   0xff00
#define  DISP_REG_GAMMA_R_RDAT   0x188
#define  DISP_REG_GAMMA_R_RDAT_OFFSET 16
#define  DISP_REG_GAMMA_R_RDAT_MASK   0xff0000
#define  DISP_REG_APB_ACC_ERR   0x188
#define  DISP_REG_APB_ACC_ERR_OFFSET 24
#define  DISP_REG_APB_ACC_ERR_MASK   0x1000000
#define  DISP_REG_CLR_APB_ACC_ERR   0x188
#define  DISP_REG_CLR_APB_ACC_ERR_OFFSET 31
#define  DISP_REG_CLR_APB_ACC_ERR_MASK   0x80000000
#define  DISP_REG_I80_IF_EN   0x200
#define  DISP_REG_I80_IF_EN_OFFSET 0
#define  DISP_REG_I80_IF_EN_MASK   0x1
#define  DISP_REG_I80_SW_MODE_EN   0x200
#define  DISP_REG_I80_SW_MODE_EN_OFFSET 1
#define  DISP_REG_I80_SW_MODE_EN_MASK   0x2
#define  DISP_REG_I80_HW_IF_EN   0x200
#define  DISP_REG_I80_HW_IF_EN_OFFSET 2
#define  DISP_REG_I80_HW_IF_EN_MASK   0x4
#define  DISP_REG_I80_CTRL_INI   0x200
#define  DISP_REG_I80_CTRL_INI_OFFSET 4
#define  DISP_REG_I80_CTRL_INI_MASK   0xf0
#define  DISP_REG_I80_IP_CLR_W1T   0x200
#define  DISP_REG_I80_IP_CLR_W1T_OFFSET 10
#define  DISP_REG_I80_IP_CLR_W1T_MASK   0x400
#define  DISP_REG_I80_RUN_W1T   0x200
#define  DISP_REG_I80_RUN_W1T_OFFSET 11
#define  DISP_REG_I80_RUN_W1T_MASK   0x800
#define  DISP_REG_I80_SW_CMD   0x204
#define  DISP_REG_I80_SW_CMD_OFFSET 0
#define  DISP_REG_I80_SW_CMD_MASK   0xffffff
#define  DISP_REG_I80_SW_CMD_RDY   0x204
#define  DISP_REG_I80_SW_CMD_RDY_OFFSET 24
#define  DISP_REG_I80_SW_CMD_RDY_MASK   0x1000000
#define  DISP_REG_I80_SW_RDY_W1T   0x204
#define  DISP_REG_I80_SW_RDY_W1T_OFFSET 31
#define  DISP_REG_I80_SW_RDY_W1T_MASK   0x80000000
#define  DISP_REG_I80_CS_STATE   0x208
#define  DISP_REG_I80_CS_STATE_OFFSET 0
#define  DISP_REG_I80_CS_STATE_MASK   0x7
#define  DISP_REG_I80_CS_IDLE   0x208
#define  DISP_REG_I80_CS_IDLE_OFFSET 3
#define  DISP_REG_I80_CS_IDLE_MASK   0x8
#define  DISP_REG_MCU_HW_TRIG   0x210
#define  DISP_REG_MCU_HW_TRIG_OFFSET 0
#define  DISP_REG_MCU_HW_TRIG_MASK   0x1
#define  DISP_REG_MCU_HW_STOP   0x210
#define  DISP_REG_MCU_HW_STOP_OFFSET 1
#define  DISP_REG_MCU_HW_STOP_MASK   0x2
#define  DISP_REG_CS_H_HW_BLK   0x210
#define  DISP_REG_CS_H_HW_BLK_OFFSET 2
#define  DISP_REG_CS_H_HW_BLK_MASK   0xc
#define  DISP_REG_MCU_565   0x210
#define  DISP_REG_MCU_565_OFFSET 4
#define  DISP_REG_MCU_565_MASK   0x10
#define  DISP_REG_HW_MCU_START_FLAG   0x210
#define  DISP_REG_HW_MCU_START_FLAG_OFFSET 6
#define  DISP_REG_HW_MCU_START_FLAG_MASK   0x40
#define  DISP_REG_HW_MCU_STOP_FLAG   0x210
#define  DISP_REG_HW_MCU_STOP_FLAG_OFFSET 7
#define  DISP_REG_HW_MCU_STOP_FLAG_MASK   0x80
#define  DISP_REG_MCU_SW_TRIG   0x214
#define  DISP_REG_MCU_SW_TRIG_OFFSET 0
#define  DISP_REG_MCU_SW_TRIG_MASK   0x1
#define  DISP_REG_CS_H_SW_IDLE   0x214
#define  DISP_REG_CS_H_SW_IDLE_OFFSET 1
#define  DISP_REG_CS_H_SW_IDLE_MASK   0x2
#define  DISP_REG_MCU_SW_TX_DONE   0x214
#define  DISP_REG_MCU_SW_TX_DONE_OFFSET 3
#define  DISP_REG_MCU_SW_TX_DONE_MASK   0x8
#define  DISP_REG_MCU_SW_TX_NUM   0x214
#define  DISP_REG_MCU_SW_TX_NUM_OFFSET 4
#define  DISP_REG_MCU_SW_TX_NUM_MASK   0xf0
#define  DISP_REG_HW_MCU_STATE   0x214
#define  DISP_REG_HW_MCU_STATE_OFFSET 8
#define  DISP_REG_HW_MCU_STATE_MASK   0xf00
#define  DISP_REG_SW_TX_CNT_RO   0x214
#define  DISP_REG_SW_TX_CNT_RO_OFFSET 12
#define  DISP_REG_SW_TX_CNT_RO_MASK   0xf000
#define  DISP_REG_SW_TX_0   0x218
#define  DISP_REG_SW_TX_0_OFFSET 0
#define  DISP_REG_SW_TX_0_MASK   0x3ff
#define  DISP_REG_SW_TX_1   0x218
#define  DISP_REG_SW_TX_1_OFFSET 16
#define  DISP_REG_SW_TX_1_MASK   0x3ff0000
#define  DISP_REG_SW_TX_2   0x21c
#define  DISP_REG_SW_TX_2_OFFSET 0
#define  DISP_REG_SW_TX_2_MASK   0x3ff
#define  DISP_REG_SW_TX_3   0x21c
#define  DISP_REG_SW_TX_3_OFFSET 16
#define  DISP_REG_SW_TX_3_MASK   0x3ff0000
#define  DISP_REG_SW_TX_4   0x220
#define  DISP_REG_SW_TX_4_OFFSET 0
#define  DISP_REG_SW_TX_4_MASK   0x3ff
#define  DISP_REG_SW_TX_5   0x220
#define  DISP_REG_SW_TX_5_OFFSET 16
#define  DISP_REG_SW_TX_5_MASK   0x3ff0000
#define  DISP_REG_SW_TX_6   0x224
#define  DISP_REG_SW_TX_6_OFFSET 0
#define  DISP_REG_SW_TX_6_MASK   0x3ff
#define  DISP_REG_SW_TX_7   0x224
#define  DISP_REG_SW_TX_7_OFFSET 16
#define  DISP_REG_SW_TX_7_MASK   0x3ff0000
#define  DISP_REG_SW_TX_8   0x228
#define  DISP_REG_SW_TX_8_OFFSET 0
#define  DISP_REG_SW_TX_8_MASK   0x3ff
#define  DISP_REG_SW_TX_9   0x228
#define  DISP_REG_SW_TX_9_OFFSET 16
#define  DISP_REG_SW_TX_9_MASK   0x3ff0000
#define  DISP_REG_SW_TX_A   0x22c
#define  DISP_REG_SW_TX_A_OFFSET 0
#define  DISP_REG_SW_TX_A_MASK   0x3ff
#define  DISP_REG_SW_TX_B   0x22c
#define  DISP_REG_SW_TX_B_OFFSET 16
#define  DISP_REG_SW_TX_B_MASK   0x3ff0000
#define  DISP_REG_SW_TX_C   0x230
#define  DISP_REG_SW_TX_C_OFFSET 0
#define  DISP_REG_SW_TX_C_MASK   0x3ff
#define  DISP_REG_SW_TX_D   0x230
#define  DISP_REG_SW_TX_D_OFFSET 16
#define  DISP_REG_SW_TX_D_MASK   0x3ff0000
#define  DISP_REG_SW_TX_E   0x234
#define  DISP_REG_SW_TX_E_OFFSET 0
#define  DISP_REG_SW_TX_E_MASK   0x3ff
#define  DISP_REG_SW_TX_F   0x234
#define  DISP_REG_SW_TX_F_OFFSET 16
#define  DISP_REG_SW_TX_F_MASK   0x3ff0000
#define  DISP_REG_I80_WRX_SW_OV   0x238
#define  DISP_REG_I80_WRX_SW_OV_OFFSET 0
#define  DISP_REG_I80_WRX_SW_OV_MASK   0x1
#define  DISP_REG_I80_RDX_SW_OV   0x238
#define  DISP_REG_I80_RDX_SW_OV_OFFSET 1
#define  DISP_REG_I80_RDX_SW_OV_MASK   0x2
#define  DISP_REG_I80_CDX_SW_OV   0x238
#define  DISP_REG_I80_CDX_SW_OV_OFFSET 2
#define  DISP_REG_I80_CDX_SW_OV_MASK   0x4
#define  DISP_REG_I80_CSX_SW_OV   0x238
#define  DISP_REG_I80_CSX_SW_OV_OFFSET 3
#define  DISP_REG_I80_CSX_SW_OV_MASK   0x8
#define  DISP_REG_I80_DAT_SW_OV   0x238
#define  DISP_REG_I80_DAT_SW_OV_OFFSET 4
#define  DISP_REG_I80_DAT_SW_OV_MASK   0x10
#define  DISP_REG_I80_WRX_SW_DAT   0x238
#define  DISP_REG_I80_WRX_SW_DAT_OFFSET 8
#define  DISP_REG_I80_WRX_SW_DAT_MASK   0x100
#define  DISP_REG_I80_RDX_SW_DAT   0x238
#define  DISP_REG_I80_RDX_SW_DAT_OFFSET 9
#define  DISP_REG_I80_RDX_SW_DAT_MASK   0x200
#define  DISP_REG_I80_CDX_SW_DAT   0x238
#define  DISP_REG_I80_CDX_SW_DAT_OFFSET 10
#define  DISP_REG_I80_CDX_SW_DAT_MASK   0x400
#define  DISP_REG_I80_CSX_SW_DAT   0x238
#define  DISP_REG_I80_CSX_SW_DAT_OFFSET 11
#define  DISP_REG_I80_CSX_SW_DAT_MASK   0x800
#define  DISP_REG_I80_DAT_SW_DAT   0x238
#define  DISP_REG_I80_DAT_SW_DAT_OFFSET 16
#define  DISP_REG_I80_DAT_SW_DAT_MASK   0xff0000
#define  DISP_REG_SRGB_TTL_EN   0x240
#define  DISP_REG_SRGB_TTL_EN_OFFSET 0
#define  DISP_REG_SRGB_TTL_EN_MASK   0x1
#define  DISP_REG_SRGB_TTL_4T   0x240
#define  DISP_REG_SRGB_TTL_4T_OFFSET 1
#define  DISP_REG_SRGB_TTL_4T_MASK   0x2
#define  DISP_REG_SRGB_TTL_G_NUM   0x240
#define  DISP_REG_SRGB_TTL_G_NUM_OFFSET 4
#define  DISP_REG_SRGB_TTL_G_NUM_MASK   0x30
#define  DISP_REG_SRGB_TTL_B_NUM   0x240
#define  DISP_REG_SRGB_TTL_B_NUM_OFFSET 6
#define  DISP_REG_SRGB_TTL_B_NUM_MASK   0xc0
#define  DISP_REG_SRGB_TTL_SW_SEQ   0x240
#define  DISP_REG_SRGB_TTL_SW_SEQ_OFFSET 8
#define  DISP_REG_SRGB_TTL_SW_SEQ_MASK   0x100
#define  DISP_REG_VTT_LITE   0x304
#define  DISP_REG_VTT_LITE_OFFSET 0
#define  DISP_REG_VTT_LITE_MASK   0x3fff
#define  DISP_REG_HTT_LITE   0x304
#define  DISP_REG_HTT_LITE_OFFSET 16
#define  DISP_REG_HTT_LITE_MASK   0x3fff0000
#define  DISP_REG_VS_STR_LITE   0x308
#define  DISP_REG_VS_STR_LITE_OFFSET 0
#define  DISP_REG_VS_STR_LITE_MASK   0x3fff
#define  DISP_REG_VS_STP_LITE   0x308
#define  DISP_REG_VS_STP_LITE_OFFSET 16
#define  DISP_REG_VS_STP_LITE_MASK   0x3fff0000
#define  DISP_REG_HS_STR_LITE   0x314
#define  DISP_REG_HS_STR_LITE_OFFSET 0
#define  DISP_REG_HS_STR_LITE_MASK   0x3fff
#define  DISP_REG_HS_STP_LITE   0x314
#define  DISP_REG_HS_STP_LITE_OFFSET 16
#define  DISP_REG_HS_STP_LITE_MASK   0x3fff0000
